Design and Hardware Implementation of QoSS - AES Processor for Multimedia applications
Zeghid Medien(b),(*), Mohsen Machhout(a), Belgacem Bouallegue(a), Lazhar Khriji(c), Adel Baganne(b), Rached Tourki(a)
Transactions on Data Privacy 3:1 (2010) 43 - 64
(a) Electronic and Micro-Electronic Laboratory, Faculty of Sciences of Monastir, 5000, Tunisia.
(b) Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance (Lab-STICC), CNRS: FRE2734-University of South Brittany, Lorient, France.
(c) ATSI- Research Unit, ISSATSO, University of Sousse, Tunisia.
e-mail:medien.zeghid @fsm.rnu.tn; ; ; ; adel.baganne @univ-ubs.fr;
For real-time applications, there are several factors (time, cost, power) that
are moving security considerations from a function centric perspective into a system
architecture (hardware/software) design issue. Advanced Encryption Standard (AES) is
used nowadays extensively in many network and multimedia applications to address
security issues. The AES algorithm specifies three key sizes: 128, 192 and 256 bits offering
different levels of security. To deal with the amount of application and intensive
computation given by security mechanisms, we define and develop a QoSS (Quality of
Security Service) model for reconfigurable AES processor. QoSS has been designed and
implemented to achieve a flexible trade-off between overheads caused by security services
and system performance. The proposed architecture can provide up to 12 AES
block cipher schemes within a reasonable hardware cost. We envisage a security vector
in a fully functional QoSS request to include levels of service for the range of security
service and mechanisms. Our unified hardware can run both the original AES algorithm
and the extended AES algorithm (QoSS-AES). A novel on-the-fly AES encryption/
decryption design is also proposed for 128- , 192- , and 256-bit keys.
The performance of the proposed processor has been analyzed in an MPEG4 video
compression standard. The results revealed that the QoSS-AES processor is well suited
to provide high security communication with low latencies. In our implementation
based on Xilinx Virtex FPGAs, speed/area/power results from these processors are analyzed
and shown to compare favorably with other well known FPGA based implementations.